NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules

By Amin Farmahini Farahani, Jung Ho Ahn, Katherine Morrow, Nam Sung Kim. International Symposium on High-Performance Computer Architecture, 2015

295 citations recorded by the source corpus.

Energy consumed for transferring data across the processor memory hierarchy constitutes a large fraction of total system energy consumption, and this fraction has steadily increased with technology scaling. In this paper, we propose near-DRAM acceleration (NDA) architectures, which process data using accelerators 3D-stacked on DRAM devices comprising off-chip main memory modules. NDA transfers most data through high-bandwidth and low-energy 3D interconnects between accelerators and DRAM devices instead of low-bandwidth and high-energy off-chip interconnects between a processor and DRAM devices, substantially reducing energy consumption and improving performance. Unlike previous near-memory processing architectures, NDA is built upon commodity DRAM devices; apart from inserting through-silicon vias (TSVs) to 3D-interconnect DRAM devices and accelerators, NDA requires minimal changes to the commodity DRAM device and standard memory module architectures. This allows NDA to be more easily adopted in both existing and emerging systems. Our experiments demonstrate that, on average, our NDA-based system consumes 46% (68%) lower (data transfer) energy at 1.67× higher performance than a system that integrates the same accelerator logic within the processor itself.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/f72fe87b47bf219689e3975727241bdf919675d3

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Citations in the corpus

RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing (2019, background): “Although customized instructions have been proposed before [5], [22], [81], our solution is the first one to directly deal with the C/A bandwidth limitation using DDR command compression that enables up to 8× bandwidth expansion for small-sized embedding vectors (i.”
PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning (2017, background): “A recent study [14] showed that data movements between CPUs and off-chip memory consumes two orders of magnitude more energy than a floating point operations.”
DRISA: A DRAM-based Reconfigurable In-Situ Accelerator (2017, background): “• Processing-in-Memory Architectures: On one hand, there is plenty of recent work on PIM [10, 12, 16, 18, 20, 30, 32, 34, 36, 42, 46, 52, 53, 67, 73, 73, 75, 76, 88, 93, 95] that built lightweight processors, reconfigurable or application-specific logics in the logic die of HMC [74] or HBM [58].”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “The second approach takes advantage of the design of emerging 3D-stacked memory technologies to enable PIM in a more general-purpose manner [7, 34, 35, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 72, 73, 74, 75, 77, 87, 88, 89, 91].”
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