ZSim: fast and accurate microarchitectural simulation of thousand-core systems

By Daniel Sánchez, Christos Kozyrakis. International Symposium on Computer Architecture, 2013

650 citations recorded by the source corpus.

Architectural simulation is time-consuming, and the trend towards hundreds of cores is making sequential simulation even slower. Existing parallel simulation techniques either scale poorly due to excessive synchronization, or sacrifice accuracy by allowing event reordering and using simplistic contention models. As a result, most researchers use sequential simulators and model small-scale systems with 16-32 cores. With 100-core chips already available, developing simulators that scale to thousands of cores is crucial. We present three novel techniques that, together, make thousand-core simulation practical. First, we speed up detailed core models (including OOO cores) with instruction-driven timing models that leverage dynamic binary translation. Second, we introduce bound-weave, a two-phase parallelization technique that scales parallel simulation on multicore hosts efficiently with minimal loss of accuracy. Third, we implement lightweight user-level virtualization to support complex workloads, including multiprogrammed, client-server, and managed-runtime applications, without the need for full-system simulation, sidestepping the lack of scalable OSs and ISAs that support thousands of cores. We use these techniques to build zsim, a fast, scalable, and accurate simulator. On a 16-core host, zsim models a 1024-core chip at speeds of up to 1,500 MIPS using simple cores and up to 300 MIPS using detailed OOO cores, 2-3 orders of magnitude faster than existing parallel simulators. Simulator performance scales well with both the number of modeled cores and the number of host cores. We validate zsim against a real Westmere system on a wide variety of workloads, and find performance and microarchitectural events to be within a narrow range of the real system.

Subfields: Hardware and Architecture, Management Science and Operations Research

View Paper: https://www.semanticscholar.org/paper/d9c91cd78453345e84db52bea42294acc2f85223

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In Hardware and Architecture

In Management Science and Operations Research

Christos Kozyrakis

Citations in the corpus

TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory (2017, methodology): “Given the timing characteristics of the NN accelerators and the memory channels/vaults, we use zsim [37] to evaluate the performance and in particular the impact of the limited memory bandwidth.”
An Evaluation of High-Level Mechanistic Core Models (2014, methodology): “…sampling [Sherwood et al. 2002; Wunderlich et al. 2003; Ardestani and Renau 2013; Carlson et al. 2013, 2014], and simulation acceleration through software optimization [Sanchez and Kozyrakis 2013] and FPGA hardware [Krasnov et al. 2007; Chiou et al. 2007; Chung et al. 2008; Pellauer et al. 2011].”
DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors (2018, methodology): “To evaluate DAWG, we use the zsim [48] executiondriven x86-64 simulator and Haswell hardware [15] for our experiments.”
DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator (2020, neutral): “DRAMsim3 can be integrated into popular CPU simulators or simulation frameworks such as SST [13], ZSim [15] and Gem5 [1] as their memory backend simulator.”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “, gem5 [216], zsim [217], gem5-gpu [218], GPGPUSim [219]) to provide a robust environment that can evaluate how various PIM architectures affect the entire compute stack, and can allow designers to identify memory, workload, and system characteristics that affect the efficiency of PIM execution.”