Overcoming the challenges of crossbar resistive memory architectures

By Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Zhang Tao, Shimeng Yu, Yuan Xie. International Symposium on High-Performance Computer Architecture, 2015

327 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/1bb29cdeab20f4f5d739aacbb403e3751ca15f3b

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Naveen Muralimanohar
2. Rajeev Balasubramonian
3. Vivek Srikumar

In Electrical and Electronic Engineering

1. John Paul Strachan
2. R. S. Williams
3. Ali Shafiee
4. Miao Hu
5. Rajeev Balasubramonian
6. Naveen Muralimanohar
7. Shimeng Yu
8. J. Joshua Yang

Citations in the corpus

• ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars (2016, background): “Memristors [66] have been primarily targeted as main memory devices [25], [74], [77].”
• PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory (2016, unknown): “Most prior work exploits ReRAM either as DRAM/flash replacement [20], [28], [40] or as synapses for NN computation [10], [11], [12], [13], [38].”