Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design

By Brian D. Olson, D. Ball, K. Warren, Lloyd W. Massengill, N. Haddad, Scott Doyle, Dale McMorrow. IEEE Transactions on Nuclear Science, 2005

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The contribution of nuclear reactions to heavy ion single event upset cross-section measurements in a high-density SEU hardened SRAM (2005, background): “A schematic and detailed discussion of the circuit operation is provided in [12].”
Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule (2010, background): “As device scaling down proceeds, novel MCU modes are being reported as “charge sharing among memory storage nodes in the vicinity [8], [23] or bipolar effects in p-well [9], [24], [25].”
Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction (2013, methodology): “in 2005 [3], and explained by Black et al.”
Single Event Transients in Digital CMOS—A Review (2013, methodology): “[72] and 130-nm CMOS latches as described by Amusan et al.”
Monte Carlo Simulation of Single Event Effects (2010, background): “The radiation-interaction portion of the event has run its course in most structures after approximately 100 fs, whereas inverter delays in 45 nm CMOS technology are of order 10 ps.”
Charge Collection and Charge Sharing in a 130 nm CMOS Technology (2006, unknown): “The n-well voltage perturbation has also been reported by other researchers [3], [15].”