Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule

By E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo, Tadanobu Toba. IEEE Transactions on Electron Devices, 2010

548 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/401ca8016df782ea1865680bbd44ce521e9ac347

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Pradip Bose
2. David Atienza Alonso
3. Subhasish G. Mitra
4. Francky Catthoor
5. Pedro C. Diniz
6. John M. Shalf
7. Mohamed M. Sabry
8. Sarita V. Adve

In Hardware and Architecture

1. Pradip Bose
2. David Atienza Alonso
3. Subhasish G. Mitra
4. Francky Catthoor
5. Christian Engelmann
6. Franck Cappello
7. John M. Shalf
8. Mohamed M. Sabry

Citations in the corpus

• Addressing failures in exascale computing (2014, background): “Note that our estimates assume that 4-bit or larger bursts increase from 1% of all SEUs to 10% or higher between 45 nm and 11 nm technology and that the rate of bursts of 8 bits or larger increases from 0:01% of all SEUs to 1% of all SEUs (Ibe et al., 2010).”
• Memory Errors in Modern Systems: The Good, The Bad, and The Ugly (2015, background): “Per-bit SRAM transient fault rates have trended downwards in recent years [17].”
• The impact of new technology on soft error rates (2011, background): “However, SEU rate depends on the balance of critical charge and critical volume, and other authors [11] predict that SRAM cell SEU rate will continue to decline to the 22nm technology node, so our results may not be generic.”
• OCEAN (2014, background): “However, as technology scales, Single-event Multibit Upset (SMU) rate increases significantly [Ibe et al. 2010], debilitating the SECDED ECC mitigation capability.”