Charge Collection and Charge Sharing in a 130 nm CMOS Technology

By O. Amusan, A. Witulski, Lloyd W. Massengill, B. Bhuva, P. R. Fleming, M. Alles, A. Sternberg, J. Black, peixiong zhao. IEEE Transactions on Nuclear Science, 2006

397 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/39cba2cf00faa69c73acb693872a913c01f60b4f

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. R. Lacoe
2. Lloyd W. Massengill
3. Paul E. Dodd
4. K. Warren
5. Jeffrey D. Black
6. D. Fleetwood
7. Pascale Gouker
8. Véronique Ferlet-Cavrois

In Hardware and Architecture

1. R. Lacoe
2. Paul E. Dodd
3. Lloyd W. Massengill

Citations in the corpus

• Improving Integrated Circuit Performance Through the Application of Hardness-by-Design Methodology (2008, methodology): “directly from an energetic particle strike and the charge due to parasitic bipolar action [57].”
• Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits (2009, methodology): “Plot comparing charge collected by an adjacent pMOS device with/ without guard bands (after [11]).”
• Monte Carlo Simulation of Single Event Effects (2010, background): “due to charge deposition in multiple volumes [88], [89], nor can they account for parasitic coupling between sensitive volumes, as has been observed in scaled CMOS [90].”
• Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction (2013, methodology): “[70], the authors studied charge collection in two to three transistors in the same well built in 3-dimensional TCAD structures with actual transistor spacing.”