3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

By Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, Krishna C. Saraswat. Proceedings of the IEEE, 2001

1,061 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/7b8147294b4690a0786ae06b57363b5431c7b767

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

Citations in the corpus

A power-optimal repeater insertion methodology for global interconnects in nanometer designs (2002, background): “S very large-scale integration (VLSI) circuits continue to be scaled aggressively past the 180-nm technology node, performance of these ICs is being increasingly dominated by the global interconnects [1], [2].”
On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects (2009, background): “where thermal management is a critical concern [89], [90].”
Carbon nanostructures for advanced composites (2006, background): “[304] Banerjee K, Souri S J, Kapur P and Saraswat K C 2001 3D ICs: A novel chip design for improving deepsubmicrometer interconnect performance and systems-on-chip integration Proc.”
Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects (2009, background): “ital, analog, RF circuits, etc) in the same chip [143], [144].”
HotSpot: a compact thermal modeling methodology for early-stage VLSI design (2006, background): “The recently proposed stacked chip-scale packaging (SCP) [19] and 3-D IC designs [20] are also stacked-layer structures and can be easily modeled as extensions of the generic stack structure in Fig.”
3-D Topologies for Networks-on-Chip (2006, background): “Another important advantage of 3-D ICs is that this paradigm enables the integration of disparate technologies which can be non-silicon or even electro-mechanical [ 1 ].”
3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems (2009, methodology): “The silicon recrystallization approach [Fig. 2(d)] could be used for fabrication of repeaters within on-chip interconnect to alleviate interconnect delay [ 10 ], [92].”
Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs (2010, neutral): “) on a single chip [1], [2].”
A thermal-driven floorplanning algorithm for 3D ICs (2004, methodology): “Interlayer via is a via that goes through a device layer for interlayer connection [ 2 ], which has expensive fabrication costs.”
Test Challenges for 3D Integrated Circuits (2009, background): “Test Challenges for 3D Integrated Circuits Hsien-Hsin S. Lee Georgia Institute of Technology Krishnendu Chakrabarty Duke University 3D ICS PROMISE TO OVERCOME barriers in interconnect scaling by leveraging fast, dense interdie vias, thereby providing an opportunity for continued higher performance u”