A power-optimal repeater insertion methodology for global interconnects in nanometer designs

By Kaustav Banerjee, A. Mehrotra. 2002

348 citations recorded by the source corpus.

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CACTI 6.0: A Tool to Model Large Caches (2009, methodology): “The total power dissipated is the sum of three main component s ( quation 6) [3].”
Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects (2008, background): “The size of repeaters is often much larger than the minimum sized gates [33].”
On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects (2009, methodology): “Global interconnects are often designed by inserting buffers (repeaters) at regular intervals to minimize delay per unit length (τ /l) [82].”
3-D Topologies for Networks-on-Chip (2006, background): “Tradeoffs in determining these topologies are discussed and the impact of the network parameters on the resulting optimum topologies are evaluated for various network sizes.”
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0 (2007, methodology): “[4] describe a methodology to compute a repeater configuration that minimizes power while giving up performance.”