Performance evaluation and design trade-offs for network-on-chip interconnect architectures

By Partha Pratim Pande, C. Grecu, Michael Jones, A. Ivanov, R. Saleh. IEEE transactions on computers, 2005

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FPGAs in Industrial Control Applications (2011, neutral): “The latter provides reusability, well-controlled global wire delay and efficient global communication [48]-[52].”
3-D Topologies for Networks-on-Chip (2006, background): “Consequently, the network latency is only reduced by decreasing the length of the horizontal buss, as described in (18).”
Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems (2011, background): “The particular NoC switch architecture, adopted from [41] for the switches in the subnets, has three functional stages, namely, input arbitration, routing/switch traversal, and output arbitration.”
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives (2009, background): “The study in [128] presents a comparative evaluation of various NoC architectures with realistic traffic models in terms of latency, throughput, and energy.”
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation (2009, methodology): “we follow the methodology discussed in [19].”