Investigating the switching dynamics and multilevel capability of bipolar metal oxide resistive switching memory

By Shimeng Yu, Yi Wu, H. Philip Wong. 2011

283 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Materials Chemistry

View Paper: https://www.semanticscholar.org/paper/3f6100caf10fcaa9825ae2e94b76ac8353c48988

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In Electrical and Electronic Engineering

In Materials Chemistry

Citations in the corpus

Compact Modeling of Conducting-Bridge Random-Access Memory (CBRAM) (2011, background): “increase in the ramp rate would linearly increase the set voltage (also shown in other CBRAM devices [35]), and our model captures this trend well.”
A Physics-Based Compact Model of Metal-Oxide-Based RRAM DC and AC Operations (2013, methodology): “To further verify the compact model and confirm the universality, the model predictions are compared with the measured data of the TiN/HfOx /AlOx /Pt bilayer RRAM devices [28].”
Resistive Switching by Voltage-Driven Ion Migration in Bipolar RRAM—Part I: Experimental Study (2012, background): “These results can be interpreted by an increasing gap along the CF, due to the increasing final voltage in the reset sweep [24], [25].”
On the Switching Parameter Variation of Metal Oxide RRAM—Part II: Model Corroboration and Device Design Strategy (2012, result): “part II of the paper (the current paper), we corroborate the simulation results with the experimental data of HfOx-based RRAM devices [15], [16], such as the dc I–V switching characteristics”
An Electronic Synapse Device Based on Metal Oxide Resistive Switching Memory for Neuromorphic Computation (2011, background): “the pulse amplitudes can tune the resistance as effectively as exponentially varying the pulsewidth but with considerably less energy consumption [39].”
A SPICE Compact Model of Metal Oxide Resistive Switching Memory With Variations (2012, background): “Index Terms—Compact model, resistive random access memory (RRAM) conducting filament, resistive switching, temperature, variation.”
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory (2016, unknown): “There are two common approaches to improve the density and reduce the cost of ReRAM: multi-layer crossbar architecture [25], [26], [27], [28] and multi-level cell (MLC) [29], [30], [31].”