PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory

By Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, Yuan Xie. 2016

621 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Electrical and Electronic Engineering

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Artificial Intelligence

1. Carole-Jean Wu
2. Song Han
3. Vivienne Sze
4. Yuan Xie
5. Tien-Ju Yang
6. Yu-hsin Chen
7. Yongming Shen
8. Péter Vajda

In Electrical and Electronic Engineering

1. Song Han
2. Tien-Ju Yang
3. Vivienne Sze
4. Joel S. Emer
5. Yu-hsin Chen
6. Guoqi Li
7. Yongming Shen
8. Yuan Xie

Citations in the corpus

• FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review (2019, neutral): “ISAAC [116] and PRIME [117] have explored in-memory processing to design an acceleration architecture for neural networks.”
• A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets (2018, neutral): “There exists an abundance of architectures for CNN inference [65], [66], [67], [68], [69], [70], [71], [72], [73], [74], [75], [76], [77], [78], [79].”
• OD-SGD (2020, positive): “…memory also contributes to computation overhead reduction, Dadiannao [26] greatly accelerates the computing speed by introducing more on-chip storage, leading to much fewer accesses to main memory, while Prime [27] takes advantage of Processing-in-memory (PIM) to reduce the memory access overhead.”
• Machine Learning at Facebook: Understanding Inference at the Edge (2019, positive): “Recent work on hardware for machine learning and efficient training and inference has substantially advanced the state-of-the-art [41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77].”
• AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators (2020, neutral): “TETRIS [85], RENO [88], PRIME [86], ISAAC [87], Memristive Boltzmann Machine [89], PipeLayer [90], Atom-layer [91], ReCom [92], ReGAN [93], ReRAM ACC.”
• Neuro-Inspired Computing With Emerging Nonvolatile Memorys (2018, neutral): “Recently, architectural simulator platforms (e.g., PRIME [118], ISAAC [119], and Harmonica [120]) have been developed to support system-level design of neuromorphic accelerators, however they have limited considerations at the aforementioned nonideal device properties (i.e., they only considered the”
• PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning (2017, neutral): “Despite the recent progresses [1, 2, 16], the current schemes based on ReRAM lack important features to efficiently execute complete deep learning applications.”
• vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design (2016, neutral): “The key contributions of our work are: • This work is the first to present a detailed, quantitative analysis on GPU-based DNN training , as opposed to recent literature targeting energy-efficient accelerators for DNN inference [20, 21, 22, 23, 24, 25, 26, 27, 28, 29].”
• Scalpel: Customizing DNN pruning to the underlying hardware parallelism (2017, neutral): “For hardware-based methods, different ASIC designs [2, 5, 7, 8, 10, 14, 18, 25, 27, 33, 36, 37] and tools for accelerating DNN on existing platform have been proposed.”
• MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation (2019, positive): “However, application to larger DNNs has yet to be demonstrated, though numerous neuromorphic proposals have leveraged eNVMs, particularly using RRAMs for processing-in-memory architectures [5, 11, 61, 64].”
• Edge Computing for Autonomous Driving: Opportunities and Challenges (2019, positive): “[43] proposed a processorin-memory (PIM) architecture to accelerate CNN applications in ReRAM based main memory.”
• Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network (2017, neutral): “ISAAC [26], PipeLayer [28], and Prime [27] use resistive RAM (ReRAM) for accelerating DNNs.”
• DRISA: A DRAM-based Reconfigurable In-Situ Accelerator (2017, positive): “Some work [19, 23, 35] has relied on emerging NVMs for computing, but DRISA takes use of the mature and cost-effective DRAM process technologies.”
• The future of electronics based on memristive systems (2018, neutral): “The key computations for restricted Boltzmann machines, including the contrastive divergence most frequently used for training, are strongly dominated by fetching weight values and computing vector operations with them, similar in that sense to other machine learning systems 39 described above.”
• Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, neutral): “The second approach takes advantage of the design of emerging 3D-stacked memory technologies to enable PIM in a more general-purpose manner [7, 34, 35, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 72, 73, 74, 75, 77, 87, 88, 89, 91].”