Research Challenges for On-Chip Interconnection Networks
By John Douglas Owens, William (Bill) J. Dally, R. Ho, D. Jayasimha, S. Keckler, Li-Shiuan Peh. IEEE Micro, 2007
504 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/2e0aa5f1ee73be5afa9c8d7db85a463ee8610c3b
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- Onur Mutlu
- Thomas Moscibroda
- Yoongu Kim
- Jeremie S. Kim
- Saugata Ghose
- Mahmut Taylan Kandemir
- Rachata Ausavarungnirun
- Mor Harchol-Balter
In Hardware and Architecture
- Onur Mutlu
- Thomas Moscibroda
- Yoongu Kim
- Mor Harchol-Balter
- Mahmut Taylan Kandemir
- Saugata Ghose
- Rachata Ausavarungnirun
- Jeremie S. Kim
Citations in the corpus
- A case for bufferless routing in on-chip networks (2009, methodology): “With the arrival of chip multiprocessor systems, on-chip interconnection networks have started to form the backbone of communication between cores and cores and memory within a microprocessor chip [53, 42, 24, 6].”