A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters
By Abbas Rahimi, Igor Loi, Mohammad Reza Kakoee, Luca Benini. 2011
130 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Electronic, Optical and Magnetic Materials, Hardware and Architecture
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- Luca Benini
- Igor Loi
- Stefan Mangard
- Frank Kagan Gürkaynak
- Davide Scaramuzza
- Srinivasan Murali
- Giovanni De Micheli
In Hardware and Architecture
- Luca Benini
- Daniele Palossi
- Igor Loi
- Stefan Mangard
- Frank Kagan Gürkaynak
- Giovanni De Micheli
- Srinivasan Murali
Citations in the corpus
- A 64-mW DNN-Based Visual Navigation Engine for Autonomous Nano-Drones (2018, background): “L1 scratchpad memory through a low-latency, high-throughput logarithmic interconnect [35].”
- μDMA: An autonomous I/O subsystem for IoT end-nodes (2017, methodology): “The CPU is connected to memory, accelerator and peripheral subsystem via a low latency logarithmic interconnect [12].”
- Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms (2016, background): “The DMA features a direct connection to the TCDM to reduce power consumption by eliminating the need for an internal buffer.”
- An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics (2016, background): “A low-latency logarithmic interconnect [52] connects all processing elements to the TCDM memory, enabling fast and efficient communication among the resources of the”