Impact of CMOS technology scaling on the atmospheric neutron soft error rate

By P. Hazucha, C. Svensson. 2000

646 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture, Safety, Risk, Reliability and Quality

View Paper: https://www.semanticscholar.org/paper/0460a9058417e357ee15a4009d820b293a8be0c7

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Lloyd W. Massengill
2. Kartik Mohanram
3. Paul E. Dodd
4. Nicholas J. Wang
5. Sanjay J. Patel
6. Norbert Seifert
7. J. Schwank
8. Quming Zhou

In Hardware and Architecture

1. Paul E. Dodd
2. Lloyd W. Massengill
3. Nicholas J. Wang
4. Sanjay J. Patel
5. Kartik Mohanram
6. Norbert Seifert
7. Quming Zhou
8. Doug Burger

In Safety, Risk, Reliability and Quality

1. Kartik Mohanram

Citations in the corpus

• SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments (2001, background): “SOFT errors (also known as single-event upsets) due to -particles and cosmic ray neutrons are a growing problem for terrestrial memory and digital logic integrated circuits (ICs) as technology scaling leads to decreased cell capacitance and operating voltage [1]–[3].”
• Gate sizing to radiation harden combinational logic (2006, background): “In [12], an inverse linear relation between collected charge and doping density was determined empirically.”
• Characterization of soft errors caused by single event upsets in CMOS processes (2004, background): “The study concluded that the neutroninduced SER per bit decreases approximately as K, i.e., by a factor of 0.7 per generation [ 78 ].”
• Modeling the effect of technology trends on the soft error rate of combinational logic (2002, methodology): “This calculation is summarized with the following formula: SER Pr SER SER where SER denotes the SER value for charge ob- tained from Hazucha & Svensson’s model, !#" and " are the left and right endpoints of interval $ , and Pr %!#" is the probability that charge !”
• ReStore: symptom based soft error detection in microprocessors (2005, background): “001 per bit [11], which is a widely accepted estimate for per-bit FIT rate in SRAMs.”
• Impact of scaling on soft-error rates in commercial microprocessors (2002, background): “According to Hazucha and Svensson, the SER depends exponentially on the ratio of the critical charge and the charge-collection efficiency [11].”
• Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices (2006, methodology): “According to [16] the SER is proportional to”