Impact of scaling on soft-error rates in commercial microprocessors

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Gate sizing to radiation harden combinational logic (2006, background): “…of feedback elements (e.g., resistors and capacitors) in the gate cell to slow the propagation of voltage transients, not using dynamic logic and the removal of floating (nondriven ) nodes [32], as well as the use of local space and time redundancy for soft-error-tolerant latches [13], [22], [27].”
Single Event Transients in Digital CMOS—A Review (2013, background): “Simulated critical charge of latch designs relative to the clock edges (dynamic window of vulnerability) in the dynamic pass-gate (21164) latch and static edge-triggered (21264) latch in DEC Alpha microprocessor core logic [127].”
Characterization of soft errors caused by single event upsets in CMOS processes (2004, background): “indicated a dramatic increase in the total SER [77].”
Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices (2006, background): “αSER is more sensitive to QCRIT then the neutron-induced SER (nSER) at the corresponding operating conditions (see [ 15 ] and figure 16).”
Basic mechanisms and modeling of single-event upset in digital microelectronics (2003, methodology): “Another method includes the choice of data path latches to include static or keeper-based designs [149].”