A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor

By Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin. Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36., 2003

1,074 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/346781aad1d2a65db2f3be1e6db1742070f4ee84

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Citations in the corpus

Informed Microarchitecture Design Space Exploration Using Workload Dynamics (2007, positive): “In addition, we built the Architecture Vulnerability Factor (AVF) analysis methods proposed in [19, 20] to estimate processor microarchitecture vulnerability to transient faults.”
Memory Errors in Modern Systems: The Good, The Bad, and The Ugly (2015, background): “, AVF analysis [25]) is critical to ensuring a resilient system design.”
The soft error problem: an architectural perspective (2005, neutral): “Mukherjee, et al. [10] introduced the concept of architecturally correct execution (ACE) to compute the SDC AVF of such struc- tures.”
Techniques to reduce the soft error rate of a high-performance microprocessor (2004, methodology): “Our earlier paper [18] provides a detailed breakdown of FDD and TDD instructions tracked via both registers and memory.”
SWIFT: software implemented fault tolerance (2005, result): “These results are in accordance with previous research [27, 9] which observed that many faults injected into programs do not result in incorrect output.”
The case for lifetime reliability-aware microprocessors (2004, methodology): “Scaling decreases lifetime reliability by shrinking the thickness of gate and inter layer dielectrics, increasing current density in interconnects, and by raising processor temperature which exponentially accelerates wear-out failures.”
VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects (2008, background): “However, architectural vulnerability factors (AVFs) [22] could be applied to model these masking effects if desired.”
Shoestring: probabilistic soft error reliability on the cheap (2010, methodology): “CRAFT [26] and PROFIT [26] improve upon the SWIFT solution by leveraging additional hardware structures and architectural vulnerability factor (AVF) analysis [18], respectively.”
BlueGene/L Failure Analysis and Prediction Models (2006, background): “Firstly, transient hardware failures are increasing, not just in memory structures and communication paths, but also in combinational circuits [17, 19].”
ReStore: symptom based soft error detection in microprocessors (2005, background): “by dead or other transitively dead instructions), or a part of prefetch instructions [21].”
Characterizing the effects of transient faults on a high-performance processor pipeline (2004, methodology): “[21] introduced a method to compute Architectural Vulnerability Factors for various processor components and IA-64 software through analysis.”