Techniques to reduce the soft error rate of a high-performance microprocessor

By Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt. Proceedings. 31st Annual International Symposium on Computer Architecture, 2004., 2004

300 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/01e499b6cf6b89babe390503e30e20d6628ddc39

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Nicholas J. Wang
2. Sanjay J. Patel

In Hardware and Architecture

1. Nicholas J. Wang
2. Sanjay J. Patel
3. Chris Mason

Citations in the corpus

• ReStore: symptom based soft error detection in microprocessors (2005, background): “[30] reduce the exposure of instructions to soft errors by squashing instructions upon encountering long latency events like cache misses.”
• Silent Data Corruptions at Scale (2021, background): “There are several studies evaluating the techniques to reduce soft error rate within processors [33], [29], we can extend these techniques to repeatable SDCs which can occur at a higher rate.”