Design of High-Performance Microprocessor Circuits

By Anantha P. Chandrakasan, W. Bowhill, F. Fox. 2001

804 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/6ebe376be0d9ea698ec46341e98fd9634f68e571

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In Electrical and Electronic Engineering

Citations in the corpus

Dynamic voltage scaling with links for power optimization of interconnection networks (2003, background): “Based on the current circuit technology [2, 3, 7, 13, 22], the latency of voltage (frequency) transition between adjacent levels is set to 10 s (100 link clock cycles).”
A technique to build a secret key in integrated circuits for identification and authentication applications (2004, background): “Electromigration and hot-carrier effects cause long-term degradation of the reliability of interconnects and transistors [3].”
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads (2002, background): “Introduction Power consumption has become an overriding constraint for microprocessor designs, not only in mobile environments, but in desktop and server applications as well.”
Towards Efficient Wireless Video Sensor Networks: A Survey of Existing Node Architectures and Proposal for A Flexi-WVSNP Design (2011, background): “(For general background on microprocessor design and their power-efficient design and operation we refer to [ 42 ]–[46].)”
Leakage Current: Moore's Law Meets Static Power (2003, methodology): “For our purposes, a simplification of equations from Chandrakasan, Bowhill, and Fox5 is sufficient to illustrate the key factors: ( 5 )”
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS (2005, background): “Similarly, V TRIPRD can be obtained by solving [14] I dsatNL (V gate = V TRIPRD ,V drain = V TRIPRD ,V source = gnd) ≈ I dsatPL (V gate = V TRIPRD ,V drain = V TRIPRD ,V source = V DD ) +I dsatAXL (V gate = V DD ,V drain = V DD ,V source = V TRIPRD ).”
Scaling of stack effect and its application for leakage reduction (2001, background): “The above equation assumes that the resulting Vds > 3kT/q [6].”
Temperature and supply Voltage aware performance and power modeling at microarchitecture level (2005, methodology): “We characterize the temperature and voltage scaling of I avg based on the following BSIM4 subthreshold leakage current model [4]:”
Leakage current reduction in CMOS VLSI circuits by input vector control (2004, background): “This can be done using some high threshold transistors called sleep transistors [17].”