Modeling line edge roughness effects in sub 100 nanometer gate length devices
By P. Oldiges, Qinghuang Lint, Karen Petrillot, Martha Sánchez, M. Ieong, M. Hargrove. International Conference on Simulation of Semiconductor Processes and Devices, 2000
152 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/f5a3020a932b5104579dfdadbe17d7769c462cf5
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Electrical and Electronic Engineering
- Asen Asenov
- Gareth Roy
- Andrew R. Brown
- Xingsheng Wang
- Savas Kaya
- John H. Davies
- Fikru Adamu-Lema
- Scott Roy
Citations in the corpus
- An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling (2001, background): “A negligible effect in the past has now become a significant contributor to the off-state leakage budget and short-channel effect (SCE) control for sub-100-nm gate length devices [1], [2].”
- Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study (2011, background): “line edge roughness (LER) [19]–[24], poly-silicon granularity [25]–[27], and random grain orientation in the high-κ dielectric [28].”
- Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness (2003, methodology): “For shorter correlation lengths and/or large thermal budgets this assumption may not be 100% accurate [ 10 ] but could be considered as a worst-case scenario.”
- Impact of Line-Edge Roughness on FinFET Matching Performance (2007, background): “The impact of gate-LER on parameter fluctuations and yield of bulk MOSFETs has been explored through 2-D and 3-D device simulations and predicted to become significant for channel lengths below 20 nm [7], [8].”