An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling

By C. H. Diaz, H. Tao, Y. Ku, A. Yen, K. Young. IEEE Electron Device Letters, 2001

169 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/5e022078dd254551ea6af2295c444020595ff9a5

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In Electrical and Electronic Engineering

1. Asen Asenov
2. Andrew R. Brown
3. Savas Kaya
4. Yu-Chih Tseng
5. S. Darling
6. Gareth Roy
7. John H. Davies
8. Xingsheng Wang

Citations in the corpus

• Block Copolymer Nanostructures for Technology (2010, background): “are: increased transistor leakage [57] (large stand-by power consumption), spread in threshold voltage [58] (decreased distinction between the digital 1s and 0s), and reduced read/write margin in a”
• Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs (2006, unknown): “roughness (LER) [10]–[13], and oxide-thickness variations (OTV) [14], [15].”
• Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness (2003, background): “Previous work on the simulation of LER effects have been focused mainly on the LER related degradation in the ratio [10], [18], [20], [21].”