Impact of Line-Edge Roughness on FinFET Matching Performance

By E. Baravelli, Abhisek Dixit, R. Rooyackers, Malgorzata Jurczak, Nicolò Speciale, K. D. Meyer. IEEE Transactions on Electron Devices, 2007

147 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/7c90a50ea44de7beb80f66f56ab6dba80ac2bdc0

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In Electrical and Electronic Engineering

1. Asen Asenov
2. Andrew R. Brown
3. Xingsheng Wang
4. Gareth Roy

Citations in the corpus

• Statistical variability and reliability in nanoscale FinFETs (2011, background): “The 3D FinFET architecture, adopted by Intel in the upcoming 22nm generation, which tolerates low channel doping is, in part, a response to the requirement for reducing the statistical variability in nanoscale transistors [3][4].”