Matthias Gries
Hardware and Architecture · 2004–2011
A researcher in the Science corpus: 3 papers; trusts 6 researchers and is trusted by 3 researchers here, as inferred from the citation graph.
Subfields
- Hardware and Architecture — 12 citations into it; #645 of 1,551 by trust here, #1,384 by citations
- Computer Networks and Communications — 8 citations into it; #4,751 of 9,886 by trust here, #8,543 by citations
Whom Matthias Gries trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
- Fred W. Glover
- Kurt Keutzer
- Todd M. Austin
- Manuel Laguna
- Jan M. Rabaey
- Eckart Zitzler
- Lothar Thiele
- Edward A. Lee
Who trusts Matthias Gries overall
Papers from Matthias Gries's perspective
Ordered by how strongly the researchers Matthias Gries trusts endorse each paper. Same corpus, a different order for every researcher.
- Performance assessment of multiobjective optimizers: an analysis and review (IEEE Transactions on Evolutionary Computation)
- Taming heterogeneity - the Ptolemy approach (Proceedings of the IEEE)
- Addressing the system-on-a-chip interconnect woes through communication-based design (Proceedings - Design Automation Conference)
- Metropolis: An Integrated Electronic System Design Environment (Computer)
- Tabu Search
- MiBench: A free, commercially representative embedded benchmark suite (Proceedings of the Fourth Annual IEEE International Workshop on Workload Characterization. WWC-4 (Cat. No.01EX538))
- A general framework for analysing system properties in platform-based embedded system designs (2003 Design, Automation and Test in Europe Conference and Exhibition)
- The Art of Computer Programming
- SimpleScalar: An Infrastructure for Computer System Modeling (Computer)
- System-level design: orthogonalization of concerns andplatform-based design (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.)
Their papers
- A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS (2010) — 714 citations
- Methods for evaluating and covering the design space during early design development (2004) — 330 citations
- A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling (2011) — 420 citations