Analysis of dynamic voltage/frequency scaling in chip-multiprocessors

By Sebastian Herbert, Diana Marculescu. Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07), 2007

394 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/5481a101ad02258f09b681d3cec3be6356f5344d

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Roberto Bruschi
2. Josep Torrellas
3. David M. Brooks
4. Gu-Yeon Wei
5. Franco R. Davoli
6. Radu Teodorescu
7. Raffaele Bolla
8. Flavio Cucchietti

In Electrical and Electronic Engineering

1. Gu-Yeon Wei
2. David M. Brooks
3. Roberto Bruschi
4. Josep Torrellas
5. Franco R. Davoli
6. Radu Teodorescu
7. Raffaele Bolla
8. Flavio Cucchietti

In Hardware and Architecture

1. Gu-Yeon Wei
2. David M. Brooks
3. Josep Torrellas
4. Radu Teodorescu

Citations in the corpus

• Energy Efficiency in the Future Internet: A Survey of Existing Approaches and Trends in Energy-Aware Fixed Network Infrastructures (2011, background): “These methods range among predictive techniques [35] and dynamic schemes [36] [37] [38] [39], which were studied for disk drives [40], processors [41] [42] [43], and other components.”
• Thread motion: fine-grained power management for multi-core systems (2009, background): “[9] reinforce the benefits of DVFS, but observe that hardware, per-core VF islands are not cost effective.”
• Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors (2008, background): “[10] S. Herbert and D. Marculescu, Analysis of dynamic volt­age/frequency scaling in chip-multiprocessors, in International Sym­posium on Low Power Electronics and Design, August 2007.”