The case for lifetime reliability-aware microprocessors

By Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers. Proceedings. 31st Annual International Symposium on Computer Architecture, 2004., 2004

462 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/480b96bc2bcc286906509cba3efa8a68c80b8550

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In Electrical and Electronic Engineering

1. Jin Qin
2. Subhasish G. Mitra
3. Bipul Chandra Paul
4. Xiaojun Li
5. Joseph B. Bernstein

Citations in the corpus

• Circuit Failure Prediction and Its Application to Transistor Aging (2007, methodology): “Prior work on Dynamic Reliability Management (DRM) [Simunic 04, Srinivasan 04a, 04b, 05, Urmanov 04] has similarities with the circuit failure prediction technique in this paper at a coarsegrained level.”
• Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation (2008, methodology): “The original Wu model (power-law voltage acceleration and non-Arrhenius temperature acceleration) has been implemented in the Reliability Aware Micro-Processor design tool jointly developed by UIUC and IBM for long-term processor-reliability prediction [35], [ 36 ].”