Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout
By B. Doyle, B. Boyanov, Supriyo Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, R. Chau. 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407), 2003
233 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/a8cd7bb6423e632962fb31929a4db5331dc3dd38
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Citations in the corpus
- High-performance CMOS variability in the 65-nm regime and beyond (2006, unknown): “The Tri-Gate [ 43 ] structure is a short FinFET with thin gate dielectric on top of the fin as well as on the sides.”
- Silicon CMOS devices beyond scaling (2006, background): “Width Height Height HeightWidth Width Length Length Length Tri-Gate FinFET SOI/planar Figure 13 Relative delay for an unloaded fan-out-of-1 ring oscillator, normalized to a PDSOI device of same length.”
- Soft Error Susceptibilities of 22 nm Tri-Gate Devices (2012, methodology): “M ULTI-GATE FETs, such as FinFETs and Tri-Gate FETs have long been advertised as the most promising candidates to extendCMOS scaling [1], [2].”
- Considerations for Ultimate CMOS Scaling (2012, background): “sides and the top [58]–[60]), Pi-Gates (the side gates extend”