PacketShader: a GPU-accelerated software router

By Sangjin Han, K. Jang, Kyoungsoo Park, Sue B. Moon. Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication, 2010

662 citations recorded by the source corpus.

We present PacketShader, a high-performance software router framework for general packet processing with Graphics Processing Unit (GPU) acceleration. PacketShader exploits the massively-parallel processing power of GPU to address the CPU bottleneck in current software routers. Combined with our high-performance packet I/O engine, PacketShader outperforms existing software routers by more than a factor of four, forwarding 64B IPv4 packets at 39 Gbps on a single commodity PC. We have implemented IPv4 and IPv6 forwarding, OpenFlow switching, and IPsec tunneling to demonstrate the flexibility and performance advantage of PacketShader. The evaluation results show that GPU brings significantly higher throughput over the CPU-only implementation, confirming the effectiveness of GPU for computation and memory-intensive operations in packet processing.

Subfields: Computer Networks and Communications

View Paper: https://www.semanticscholar.org/paper/25f855c968af75e4617f25c71aee3cedec1dedaf

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In Computer Networks and Communications

Citations in the corpus

Accelerating Mobile Audio Sensing Algorithms through On-Chip GPU Offloading (2017, background): “Packet routing [31] and SSL encryption [37] leverage GPUs to increase processing throughput via batching of computations, but none of these works is focused on studying energy efficiency aspects which are critical for battery-powered devices.”
The eXpress data path: fast programmable packet processing in the operating system kernel (2018, methodology): “Examples of such applications include those performing single functions, such as switching [47], routing [19], named-based forwarding [28], classification [48], caching [33] or traffic generation [14].”
netmap: A Novel Framework for Fast Packet I/O (2012, background): “The PacketShader [5] I/O engine (PSIOE) is another close relative to our proposal, especially in terms of performance.”
In-band Network Telemetry via Programmable Dataplanes (2015, background): “At the mid- and low-end of the performance spectrum, CPUs [7], GPUs [8], FPGAs [1], and NPUs [3] already offer great flexibility with performance of a few tens to hundreds of Gb/s.”
The Road to SDN (2013, background): “5, 21, 38, 45, 49, 71, 73 Before beginning this story, we caution the reader”
The road to SDN: an intellectual history of programmable networks (2014, result): “SDN also relates to previous work on separating the control and data planes in computer networks.”
Design and Implementation of a Consolidated Middlebox Architecture (2012, background): “General-purpose network elements: There are many efforts to build commodity routers and switches using x86 CPUs [18, 19, 22], GPUs [23], and merchant switch silicon [27].”
IncBricks: Toward In-Network Computation with an In-Network Cache (2017, background): “Software switches (such as Click [30], Route-Bricks [22] and PacketShader [25]) are able to perform dynamic header parsing but they remain two orders of magnitude slower at switching than a hardware switch chip.”
A comprehensive survey of Network Function Virtualization (2018, background): “on specialized drivers, such feature may lead to performance degradation [122] .”
Routing or Computing? The Paradigm Shift Towards Intelligent Computer Network Packet Transmission Based on Deep Learning (2017, methodology): “As a remedy to this problem, the PacketShader architecture [3] shifts the computation needs for parallel packets processing from CPUs to GPUs as a GPU consists of many more cores compared to a CPU.”
Forwarding metamorphosis: fast programmable match-action processing in hardware for SDN (2013, methodology): “Our design performance exceeds that of CPUs by two orders of magnitude [7], and GPUs and NPUs by one order [5,9,12,29].”