Thread motion: fine-grained power management for multi-core systems

By K. Rangan, Gu-Yeon Wei, David M. Brooks. 2009

269 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture, ML Systems & Hardware

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. David M. Brooks
2. Nadathur Rajagopalan Satish
3. Pradeep K. Dubey
4. M. Smelyanskiy
5. Jatin Chhugani
6. Kim M. Hazelwood
7. Gu-Yeon Wei
8. Anthony D. Nguyen

In Electrical and Electronic Engineering

1. Gu-Yeon Wei
2. David M. Brooks
3. Changkyu Kim

In Hardware and Architecture

1. Gu-Yeon Wei
2. David M. Brooks
3. Nadathur Rajagopalan Satish
4. Pradeep K. Dubey
5. M. Smelyanskiy
6. Kim M. Hazelwood
7. Onur Mutlu
8. Abhishek Dhanotia

In ML Systems & Hardware

1. Gu-Yeon Wei
2. David M. Brooks
3. Kim M. Hazelwood
4. Svilen Kanev
5. Carole-Jean Wu

Citations in the corpus

• Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU (2010, background): “Various aspects of multi-core architectures such as cache/memory hierarchy [11], on-chip interconnect [4] and power management [37] have been studied.”
• Tradeoffs between power management and tail latency in warehouse-scale applications (2014, background): “Furthermore, in simulation, IPC variability (and, hence, potential DVFS gains) of SPEC benchmarks has been shown to decrease by more than 100× between intervals of 300 and 10K instructions [27].”