Efficient implementation of sorting on multi-core SIMD CPU architecture

By Jatin Chhugani, Anthony D. Nguyen, Victor W. Lee, William Macy, Mostafa Hagog, Yen-kuang Chen, Akram Baransi, Sanjeev Kumar, Pradeep K. Dubey. 2008

261 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Computer Networks and Communications, Hardware and Architecture, Efficiency & Compression

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Citations in the corpus

Billion-Scale Similarity Search with GPUs (2017, methodology): “Sorting networks are commonly used on SIMD architectures [13], as they exploit vector parallelism.”
Cache locality is not enough: High-Performance Nearest Neighbor Search with Product Quantization Fast Scan (2015, methodology): “D7[a[7]] D7[b[7]] D7[c[7]] D7[d[7]] .”
In-Memory Big Data Management and Processing: A Survey (2015, background): “Accelerators such as GPGPU and Xeon Phi are also considered as shared-memory scale-up parallelism. such as join [98], [114], [115], [116], [117], [118], [119], [120], [121], [122], and sort [95], [123], [124].”
Designing efficient sorting algorithms for manycore GPUs (2009, background): “23rd IEEE International Parallel and Distributed Processing Symposium, May 2009. optimized published multicore CPU sort [16] running on a 4-core 3.22 GHz Intel Q9550 processor.”
State-of-the-art in heterogeneous computing (2010, methodology): “[42] presented a sorting algorithm suitable for parallel architectures with a shared and coherent L2 cache and wide SIMD capabilities.”
Sort vs. Hash Revisited: Fast Join Implementation on Modern Multi-Core CPUs (2009, methodology): “Chhugani et al. [7] show an efﬁcient implementation of a merge sort algorithm by exploiting both TLP and DLP on recent multi-core processors.”
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU (2010, background): “Sort(Sort) [15, 39, 40] Database Gather/Scatter Across elements Compute bound”