An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness
By Sunpyo Hong, Hyesoon Kim. International Symposium on Computer Architecture, 2009
736 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/47d526abe02451421ca2ce3688d6e8b0e6967cb0
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- John Douglas Owens
- Yao Zhang
- Abhishek Dhanotia
- Akshitha Sriraman
- Sunpyo Hong
- Hyesoon Kim
- Jingfei Kong
- Ping Xiang
In Hardware and Architecture
- John Douglas Owens
- Yao Zhang
- Sunpyo Hong
- Hyesoon Kim
- Akshitha Sriraman
- Abhishek Dhanotia
- Jingfei Kong
- Ping Xiang
Citations in the corpus
- A characterization of the Rodinia benchmark suite with comparison to contemporary CMP workloads (2010, methodology): “developed an analytical model to predict GPU performance [14] and proposed metrics to represent degree of warp-level parallelism.”
- Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU (2010, background): “However, their focus is to map non-graphic app lications to GPUs in terms of algorithms and programming models Analytical models of CPUs [51] and GPUs [22] have also been proposed.”
- An integrated GPU power and performance model (2010, methodology): “2 Benchmarks To test the accuracy of our IPP system, we use the Merge benchmarks [15, 9], five additional memory bandwidth-limited benchmarks (Nmat, Dotp, Madd, Dmadd, and Mmul), and one computational intensive (i.”
- Model-driven autotuning of sparse matrix-vector multiply on GPUs (2010, background): “This skew will depend on kernel features such as the number memory operations and the number of warps in a single thread block and hardware factors such as the bandwidth and the number of banks in the memory system [10].”
- Big IoT Data Analytics: Architecture, Opportunities, and Open Research Challenges (2017, background): “To date, the memory of clusters has reached terabyte (TB) level [41].”
- A GPGPU compiler for memory optimization and parallelism management (2010, methodology): “Another way is to use an analytical performance model [ 7 ], [15] to predict the performance of each version, but this requires higher accuracy than current models.”
- Accelerometer: Understanding Acceleration Opportunities for Data Center Overheads at Hyperscale (2020, background): “model GPU execution time [56] and power requirements [57].”
- A survey on platforms for big data analytics (2014, background): “This architecture implies that for any job to be run on GPU, it has to be broken into blocks of computation that can run independently without communicating with each other [32].”
- An Overview of Internet of Things (IoT) and Data Analytics in Agriculture: Benefits and Challenges (2018, background): “This includes real-time analytics, off-line analytics, memory-level analytics, business intelligence level analytics, and massive analytics [87]–[89].”
- A quantitative performance analysis model for GPU architectures (2011, background): “Baghsorkhi et al. [8] and Hong and Kim [9] recently authored excellent studies on GPU performance modeling.”