State-of-the-art in heterogeneous computing
By André Rigland Brodtkorb, Christopher Dyken, Trond Runar Hagen, Jon Mikkelsen Hjelmervik, Olaf O. Storaasli. Scientific Programming, 2010
297 citations recorded by the source corpus.
Node level heterogeneous architectures have become attractive during the last decade for several reasons: compared to traditional symmetric CPUs, they offer high peak performance and are energy and/or cost efficient. With the increase of fine-grained parallelism in high-performance computing, as well as the introduction of parallelism in workstations, there is an acute need for a good overview and understanding of these architectures. We give an overview of the state-of-the-art in heterogeneous computing, focusing on three commonly found architectures: the Cell Broadband Engine Architecture, graphics processing units (GPUs), and field programmable gate arrays (FPGAs). We present a review of hardware, available software tools, and an overview of state-of-the-art techniques and algorithms. Furthermore, we present a qualitative and quantitative comparison of the architectures, and give our view on the future of heterogeneous computing.
Subfields: Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/d817dbfc646deebe56c8f33eeecfc0043f18160b
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Citations in the corpus
- Graphics processing unit (GPU) programming strategies and trends in GPU computing (2013, background): “This combination is known as a heterogeneous computer: the combination of traditional CPU cores and specialized accelerator cores [4].”
- Performance Analysis of Google Colaboratory as a Tool for Accelerating Deep Learning Applications (2018, background): “Besides being massively parallel, this sort of device is also energy efficient [2], [3].”
- A review on regional convection‐permitting climate modeling: Demonstrations, prospects, and challenges (2015, background): “…simulations is the evolution of hybrid or heterogeneous high-performance computing architectures where multicore CPUs are combined with accelerators (either graphic processing units (GPUs) or Many Integrated Core chip designs) on a single compute node [Brodtkorb et al., 2010; Liu et al., 2012].”