A Comparative Study on the Impacts of Interface Traps on Tunneling FET and MOSFET

By Y. Qiu, Runsheng Wang, Qianqian Huang, Ru Huang. IEEE Transactions on Electron Devices, 2014

135 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/850e1df1bc7bcdab32e58f42f02ce7db2ec40b4a

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Shubham Sahay
2. J. Madan
3. Rishu Chaujar
4. Mamidala Jagadesh Kumar
5. Uygar E. Avci
6. Ian A. Young
7. Daniel H. Morris

Citations in the corpus

• Tunnel Field-Effect Transistors: Prospects and Challenges (2015, background): “level of SS degradation in the MOSFET and TFET I-V characteristics [15].”
• Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability (2016, background): “Apart from the high electric field, hot carrier stress (HC) and positive bias temperature instability (PBTI) are also attributed to the generation of ITC [16].”
• Controlling the Drain Side Tunneling Width to Reduce Ambipolar Current in Tunnel FETs Using Heterodielectric BOX (2015, methodology): “But the unique property of ambipolar conduction in TFETs limits their utility for digital circuit applications [13], [14].”