Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors
By Lars Knoll, Qing-Tai Zhao, A. Nichau, S. Trellenkamp, S. Richter, A. Schäfer, David Esseni, Luca Selmi, K. Bourdelle, S. Mantl. IEEE Electron Device Letters, 2013
179 citations recorded by the source corpus.
Inverters based on uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field-effect transistors (TFETs) are fabricated. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n TFETs. The steep junctions formed by dopant segregation at low temperatures improve the band-to-band tunneling, resulting in higher on-currents of n- and p-TFETs of > 10 μA/μm at VDS=0.5 V. The subthreshold slope for n-channel TFETs reaches a minimum value of 30 mV/dec, and is <; 60 mV/dec over one order of magnitude of drain current. The first sSi NW complementary TFET inverters show sharp transitions and fairly high static gain even at very lowVDD=0.2 V. The first transient response analysis of the inverters shows clear output voltage overshoots and a fall time of 2 ns at VDD=1.0 V.
Subfields: Biomedical Engineering, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/6ac0154062900ca5c791b4ec09bf001720e91124
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Citations in the corpus
- Tunnel Field-Effect Transistors: State-of-the-Art (2014, background): “are given for Si in [26], [29], [31] and for InGaAs in [47].”