A scalable processing-in-memory accelerator for parallel graph processing

By Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi. International Symposium on Computer Architecture, 2015

900 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Computer Vision and Pattern Recognition, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/4bd669b70ec1d1fa2d7825bdf7a17ae7c80f4480

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Citations in the corpus

Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology (2017, background): “Recent works (e.g., [16, 17, 24, 37, 42, 47, 48, 115]) propose processing in the logic layer of 3D-stacked DRAM, which stacks DRAM layers on top of a logic layer (e.g., Hybrid Memory Cube [6, 51]).”
ASIC Clouds: Specializing the Datacenter (2016, background): “ASIC Cloud-worthy accelerators with planet-scale applicability are numerous, including those targeting graph processing [28], database servers [29], Web Search RankBoost [30], Machine Learning [31, 32], gzip/gunzip [33] and Big Data Analytics [34].”
Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks (2018, methodology): “Like prior works [3, 4, 12, 35, 65, 66], we use the memory bandwidth available to the logic layer of 3D-stacked memory as the memory bandwidth to the PIM core/accelerator.”
DRISA: A DRAM-based Reconfigurable In-Situ Accelerator (2017, background): “• Processing-in-Memory Architectures: On one hand, there is plenty of recent work on PIM [10, 12, 16, 18, 20, 30, 32, 34, 36, 42, 46, 52, 53, 67, 73, 73, 75, 76, 88, 93, 95] that built lightweight processors, reconfigurable or application-specific logics in the logic die of HMC [74] or HBM [58].”
Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories (2016, background): “For example, the internal bandwidth in the hybrid memory cube (HMC) [20] is 128 times larger than its SerDes interface [4].”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, methodology): “In our prior work, we have started identifying several applications that can benefit from PIM in graph processing frameworks [34, 35], pointer chasing [33, 62], databases [62, 70, 71, 209], consumer workloads [7], machine learning [7], and GPGPU workloads [59, 60].”
PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning (2017, background): “Recent efforts [57, 58] decouple logic and memory designs in different dies, adopting 3D stacked memories with a logic layer that encapsulates processing units to perform computation.”
Graphicionado: A high-performance and energy-efficient accelerator for graph analytics (2016, methodology): “Lastly, Tesseract [3] targets the same domain as our work, but explores different technology by implementing specific hardware extensions using the logic layer of a 3D-stacked DRAM.”
PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture (2015, background): “…itself was already studied by many researchers decades ago, it is worth revisiting it in a new context today: (1) 3D stacking technology now enables cost-effective integration of logic and memory and (2) many new applications are data-intensive and demand great amounts of memory bandwidth [1,2,32].”
GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks (2017, background): “proposed an in-memory accelerator for graph processing [13].”
TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory (2017, methodology): “The aggregated power consumption of the 16-vault T ETRIS is on average 6.94 W at 500 MHz with a maximum of 8.42 W, which is comparable to the power consumption of previous studies that placed compute capabilities in HMC stacks [2, 16, 35].”
RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing (2019, neutral): “HMC/HBM) [4], [8], [16], [20], [28]–[30], [39], [41], [43], [58].”
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory (2016, positive): “Recent efforts [2], [3], [4], [5], [58] decouple logic and memory designs in different dies, adopting 3D stacked memories with a logic layer that encapsulates processing units to perform computation, as shown in Figure 3(b).”