High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

By Navab Singh, A. Agarwal, L. Bera, T. Liow, Rong Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Lo, N. Balasubramanian and 1 more. IEEE Electron Device Letters, 2006

558 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/b33301fb2d197cc1b86910f932dfb56c0506f45c

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Biomedical Engineering

1. Yang-Kyu Choi

In Electrical and Electronic Engineering

1. Juan Pablo Duarte
2. Sung-Jin Choi
3. Navab Singh
4. Yang-Kyu Choi
5. Roy P. Paily
6. Ratul Kumar Baruah
7. Giovanni Neri

Citations in the corpus

• Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors (2011, background): “They show a steep subthreshold slope and lowered leakage current with a very short LG regime [1]‐[ 3 ].”
• Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET (2008, background): “GATE-ALL-AROUND (GAA) nanowire FET has attracted much attention for better electrostatic control as compared to other gate designs such as double- or trigated transistors [1]–[6].”