A spacer patterning technology for nanoscale CMOS

By Yang-Kyu Choi, Tsu-Jae King, Chenming Calvin Hu. 2002

218 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/3eda30140de5e4bcca921c9bfd38fc3d6d72b888

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

1. R. Joshi
2. Edward J. Nowak
3. Ching-Te Chuang
4. Thomas Ludwig
5. Kerry Bernstein
6. Ruchir Puri
7. Ingo Dr Aller
8. Keunwoo Kim

Citations in the corpus

• Turning silicon on its edge [double gate CMOS/FinFET technology] (2004, methodology): “To etch the ultrathin (TSi = 15 nm) fins, spacer lithography [sidewall image transfer (SIT)] [17], [18] is used.”