Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

By Yu Cai, Yixin Luo, Erich F. Haratsch, K. Mai, Onur Mutlu. International Symposium on High-Performance Computer Architecture, 2015

299 citations recorded by the source corpus.

Retention errors, caused by charge leakage over time, are the dominant source of flash memory errors. Understanding, characterizing, and reducing retention errors can significantly improve NAND flash memory reliability and endurance. In this paper, we first characterize, with real 2y-nm MLC NAND flash chips, how the threshold voltage distribution of flash memory changes with different retention age - the length of time since a flash cell was programmed. We observe from our characterization results that 1) the optimal read reference voltage of a flash cell, using which the data can be read with the lowest raw bit error rate (RBER), systematically changes with its retention age, and 2) different regions of flash memory can have different retention ages, and hence different optimal read reference voltages. Based on our findings, we propose two new techniques. First, Retention Optimized Reading (ROR) adaptively learns and applies the optimal read reference voltage for each flash memory block online. The key idea of ROR is to periodically learn a tight upper bound, and from there approach the optimal read reference voltage. Our evaluations show that ROR can extend flash memory lifetime by 64% and reduce average error correction latency by 10.1%, with only 768 KB storage overhead in flash memory for a 512 GB flash-based SSD. Second, Retention Failure Recovery (RFR) recovers data with uncorrectable errors offline by identifying and probabilistically correcting flash cells with retention errors. Our evaluation shows that RFR reduces RBER by 50%, which essentially doubles the error correction capability, and thus can effectively recover data from otherwise uncorrectable flash errors.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/afb839966e384b189c610d76f0b1ba37b849eb95

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Citations in the corpus

RowHammer: A Retrospective (2019, methodology): “All scaled memory technologies, including SRAM [62], [93], [120], flash [42], [45], [46], [50]–[53], [67], [165], [166], [169], [212], and hard disk drives [109], [232], [247], exhibit such disturbance problems.”
SCORE (2018, background): “They can be reduced by adjusting the read reference voltage [12] and periodically refreshing the data [14, 44].”
SSD Failures in Datacenters: What? When? and Why? (2016, background): “Several works have examined failure trends of raw ﬂash chips [4, 6, 8, 10, 15, 16, 26, 32].”