SimpleScalar: An Infrastructure for Computer System Modeling

By Todd M. Austin, E. Larson, Dan Ernst. Computer, 2002

1,748 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/989426f537434a690936fa847517914ba72324be

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

In Hardware and Architecture

Citations in the corpus

PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator (2007, background): “It supports the Alpha instruction set, as well as PISA, a MIPS-like synthetic ISA developed specifically for SimpleScalar.”
3D-Stacked Memory Architectures for Multi-core Processors (2008, methodology): “We use the SimpleScalar toolset for the x86 ISA for performance evaluation [3], and we extended it to perform cycle-level modeling of a multicore processor.”
Covert and Side Channels Due to Processor Architecture (2006, methodology): “To evaluate the performance degradation, we run a set of SPEC2000 benchmarks on the Simplescalar simulator [25].”
Graphite: A distributed parallel simulator for multicores (2010, background): “In fact, the majority of simulators available today are not parallel at all [1], [2], [3], [4], [5], potentially forcing a single core to perform all the work of hundreds of cores.”
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research (2002, methodology): “SimpleScalar [1] is one example of an execution-driven simulator [4], [8], [13] commonly used by the computer architecture research community.”
GARNET: A detailed on-chip network model inside a full-system simulator (2009, methodology): “In the past, SimpleScalar [4] was widely used in the architecture research community to evaluate uniprocessor systems.”
The worst-case execution-time problem—overview of methods and survey of tools (2008, methodology): “The Simplescalar [Austin et al. 2002] simulator among others is used.”
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation (2006, methodology): “Shared memory program constructs such as locks and barriers are modeled using a set of magic instructions implemented with the SimpleScalar annotations [1].”
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches (2009, methodology): “Our cycle-level model is built on top of the SimpleScalar toolset for x86 [2, 30].”
Methods for evaluating and covering the design space during early design development (2004, methodology): “Simulators, such as SimpleScalar [27] and SimOS [28], are specialized in certain classes of CPUs, such as MIPS-based cores.”