Jae-Joon Kim

Electrical and Electronic Engineering · with Di · 2002–2004

A researcher in the Science corpus: 2 papers; trusts 1 researcher and is trusted by 0 researchers here, as inferred from the citation graph.

Subfields

Whom Jae-Joon Kim trusts overall

Their strongest outbound trust, strongest first, inferred from their citations.

  1. Yuan Taur

Papers from Jae-Joon Kim's perspective

Ordered by how strongly the researchers Jae-Joon Kim trusts endorse each paper. Same corpus, a different order for every researcher.

  1. Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs
  2. Sub-50 nm P-channel FinFET
  3. No exponential is forever: but "Forever" can be delayed! [semiconductor industry] (2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.)
  4. Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation (Digest. International Electron Devices Meeting,)
  5. Robust subthreshold logic for ultra-low power operation (IEEE Transactions on Very Large Scale Integration (vlsi) Systems)
  6. AND T
  7. Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors (2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104))
  8. Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs (IEEE Electron Device Letters)
  9. On the performance limits for Si MOSFETs: a theoretical study
  10. An analytical solution to a double-gate MOSFET with undoped body

Their papers