Sub-50 nm P-channel FinFET
By Xuejue Huang, C. Kuo, D. Hisamoto, Leland Chang, Jakub Kedzierski, E. Anderson, H. Takeuchi, Yang-Kyu Choi, K. Asano, V. Subramanian and 2 more. 2001
316 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/177aa9e5bb0ed552e3eabc131eb7da252de772d9
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In Electrical and Electronic Engineering
- Heike E. Riel
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Citations in the corpus
- FinFET design considerations based on 3-D simulation and analytical modeling (2002, background): “In order to suppress SCE, the fin thickness has to be less than one third of the channel length [ 15 ].”
- Toward Nanowire Electronics (2008, methodology): “With channel lengths of transistors in the nanometer regime, replacing the active component of a field-effect transistor (FET) device by a semiconducting nanomaterial occurs to be a logic choice [1]–[10].”
- High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices (2006, methodology): “Considering the volume inversion in the channel [18] and to facilitate comparison with previous works [4], [7], [9]–[11],”
- Double gate-MOSFET subthreshold circuit for ultralow power applications (2004, background): “In spite of process difficulty, the S/D of DG-MOSFETs is often raised to reduce the S/D resistance of DG-MOSFETs [15], [16].”