Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation

By J. Kedzierski, Edward J. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy and 14 more. Digest. International Electron Devices Meeting,, 2002

181 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/822e0468b55d1e8acec8286d4ab79224667cf3f9

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In Electrical and Electronic Engineering

1. Kaushik Roy
2. Jae-Joon Kim
3. Evgeni P. Gusev
4. A. Dixit
5. Yonghong Tian

Citations in the corpus

• Analysis of the parasitic S/D resistance in multiple-gate FETs (2005, background): “These devices have been reported to achieve the target performance [12] with CMOS compatible processing.”
• Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia (2008, background): “2 eV [74] for electrons and holes in order to outperform the ohmic S/D”
• Double gate-MOSFET subthreshold circuit for ultralow power applications (2004, background): “We match of each device with different by adjusting metal gate workfunctions [14].”
• Hybrid-orientation technology (HOT): opportunities and challenges (2006, background): “[1]–[3], Vertical MOSFETs [4], [5], high-k dielectric and/or metal gate [6]–[9], and most of all, various approaches for carrier-mobility enhancement.”
• Turning silicon on its edge [double gate CMOS/FinFET technology] (2004, methodology): “TEM cross section of metal-gate DG-FinFET using nickel-silicide as the gate electrode (reprinted from [8]).”