NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

By Pai-Yu Chen, Xiaochen Peng, Shimeng Yu. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018

455 citations recorded by the source corpus.

Neuro-inspired architectures based on synaptic memory arrays have been proposed for on-chip acceleration of weighted sum and weight update in machine/deep learning algorithms. In this paper, we developed NeuroSim, a circuit-level macro model that estimates the area, latency, dynamic energy, and leakage power to facilitate the design space exploration of neuro-inspired architectures with mainstream and emerging device technologies. NeuroSim provides flexible interface and a wide variety of design options at the circuit and device level. Therefore, NeuroSim can be used by neural networks (NNs) as a supporting tool to provide circuit-level performance evaluation. With NeuroSim, an integrated framework can be built with hierarchical organization from the device level (synaptic device properties) to the circuit level (array architectures) and then to the algorithm level (NN topology), enabling instruction-accurate evaluation on the learning accuracy as well as the circuit-level performance metrics at the run-time of online learning. Using multilayer perceptron as a case-study algorithm, we investigated the impact of the “analog” emerging nonvolatile memory (eNVM)’s “nonideal” device properties and benchmarked the tradeoffs between SRAM, digital, and analog eNVM-based architectures for online learning and offline classification.

Subfields: Cellular and Molecular Neuroscience, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/eb878bd0679579e2cbaadb55b4134d193c89c266

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Cellular and Molecular Neuroscience

1. Huaqiang Wu
2. Bin Gao
3. He Qian
4. Shimeng Yu
5. Daniele Ielmini
6. H. Philip Wong

In Electrical and Electronic Engineering

1. Shimeng Yu
2. Huaqiang Wu
3. Bin Gao
4. He Qian
5. Jianshi Tang
6. Wenqiang Zhang
7. Daniele Ielmini
8. H. Philip Wong

Citations in the corpus

• Neuro-inspired computing chips (2020, methodology): “Circuit-level macro-model simulator platforms can be used to estimate area, latency, and energy of synapse–neuron cores for on-chip learning or inference with realistic device properties 81 .”
• Hardware implementation of memristor-based artificial neural networks (2024, unknown): “For benchmarking a device or a chip, it is essential to evaluate the accuracy of standard deep neural network models like VGG 89 and ResNet 90 on CIFAR and ImageNet dataset by utilizing architecture-levelsimulationandrealistichardwarestatistics 91,92 .”