FinFET scaling to 10 nm gate length
By B. Yu, Leland Chang, Shibly S. Ahmed, H. Wang, S. Bell, Chih-Yuh Yang, C. Tabery, C. Ho, Q. Xiang, Tsu-Jae King and 4 more. Digest. International Electron Devices Meeting,, 2002
626 citations recorded by the source corpus.
View Paper: https://www.semanticscholar.org/paper/d0c3e2de60a8f5abff147e2a32072f400b09d620
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
- M. Anantram
- Vishal P. Trivedi
- Alexei Svizhenko
- Sandra E. Thompson
- E. Baravelli
- Min Yang
- Robert S. Chau
- Abhisek Dixit
Citations in the corpus
- Nanoscale FinFETs with gate-source/drain underlap (2005, background): “HE concept of “nonoverlapped” gate-source/drain (G-S/D) with low-doped channel was recently suggested [ 1 ] to facilitate the scaling of bulk-Si MOSFETs to nm gate lengths.”
- In search of "Forever," continued transistor scaling one new material at a time (2005, background): “the majority of future transistor work has focused on making a better intrinsic switch [1]–[3], [19], [67], [68].”
- Impact of Line-Edge Roughness on FinFET Matching Performance (2007, background): “On the other hand, the introduction of alternative transistor architectures, such as FinFET, can significantly improve transistor performance at short dimensions [1], [2].”
- Role of scattering in nanotransistors (2002, background): “It is believed that devices with channel lengths equal to 10 nm may become possible in research laboratories [4].”
- Analysis of the parasitic S/D resistance in multiple-gate FETs (2005, background): “More refined members of this family of multiple-gate field-effect transistors (MuGFETs) are FinFETs [5], tri-gate FETs [6], Omega-FETs [7], Pi-gate FETs [8], and gate-all-around FETs Manuscript received November 5, 2004; revised February 17, 2005.”
- Hybrid-orientation technology (HOT): opportunities and challenges (2006, background): “[1]–[3], Vertical MOSFETs [4], [5], high-k dielectric and/or metal gate [6]–[9], and most of all, various approaches for carrier-mobility enhancement.”
- A Tunnel FET for $V_{DD}$ Scaling Below 0.6 V With a CMOS-Comparable Performance (2011, unknown): “around (GAA) metal–oxide–semiconductor field-effect transistors (MOSFETs) [1], fin-shaped FET [2], carbon nanotube FET,”