Analysis of the parasitic S/D resistance in multiple-gate FETs
By A. Dixit, Anil Kottantharayil, N. Collaert, M. Goodwin, Malgorzata Jurczak, K. D. Meyer. IEEE Transactions on Electron Devices, 2005
375 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/0b9df1e29d295d4c5874059e281db157852809b7
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
- A. Verhulst
- William G. Vandenberghe
- K. Maex
- Guido Groeseneken
- R. Rooyackers
- S. Gendt
- M. Heyns
- K. D. Meyer
Citations in the corpus
- Impact of Line-Edge Roughness on FinFET Matching Performance (2007, background): “In order to decrease FinFET series resistance and thereby increase ION, highly doped S/D extensions are sought [ 17 ].”
- RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs (2011, background): “[4] A. Kranti and G. A. Armstrong, “Source/drain extension region engineering in FinFETs for low-voltage analog applications,” IEEE Electron Device Lett., vol. 28, no. 2, pp. 139–141, Feb. 2007.”
- Complementary Silicon-Based Heterostructure Tunnel-FETs With High Tunnel Rates (2008, background): “The same applies to the source and drain resistances of narrow fin-based or nanowire-based FET configurations [19].”