Leveraging Optical Technology in Future Bus-based Chip Multiprocessors

By Nevin Kirman, Meyrem Kirman, R. Dokania, José F. Martínez, A. Apsel, Matthew A. Watkins, D. Albonesi. Micro, 2006

311 citations recorded by the source corpus.

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

Flattened Butterfly Topology for On-Chip Networks (2007, background): “For example, on-chip optical signalling [17] and on-chip high-speed signalling [13] attempt to provide signal propagation velocities that are close to the speed of light while providing higher bandwidth for on-chip communications.”
Firefly: illuminating future network-on-chip with nanophotonics (2009, background): “One such implementation is single-write-multiple-read (SWMR) nanophotonic buses [24] as shown in Figure 4(a).”
Silicon-photonic clos networks for global on-chip communication (2009, background): “, crossbars [7, 15] and meshes [13]) have been developed bottom-up using fixed device technology parameters as drivers.”
Corona: System Implications of Emerging Nanophotonic Technology (2008, unknown): “Recent proposals for optical networks in chip multiprocessors include a hierarchical multi-bus with optical global layer [15] and an optical, circuit-switched, mesh-based network managed by electrical control packets [28].”