Double-gate CMOS: symmetrical- versus asymmetrical-gate devices

By Keunwoo Kim, Jerry G. Fossum. 2001

204 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/98f7659b23405e81fccb447f2238cb993c58851d

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

Citations in the corpus

Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric (2007, methodology): “3, which compares the Id–Vg characteristics of an optimized asymmetrical DG MOSFET from [19] with those of a simulated DG Tunnel FET, being proposed for the first time in this paper.”
Nanoscale FinFETs with gate-source/drain underlap (2005, background): “, fully depleted (FD) silicon-on-insulator (SOI) [4] and double-gate (DG) [5] MOSFETs, having ultrathin Si channels/bodies (UTBs) for SCE control, are being checked for scalability, and, because of technological limitations, the UTBs must be left undoped.”
Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs (2001, background): “This is because of the closer distance, and therefore higher capacitance, between the second gate (on the RHS of Fig. 2) and the first channel (on the left-hand side of Fig. 2) [ 4 ], which will be discussed in more detail in the next section.”
Physical insights regarding design and performance of independent-gate FinFETs (2005, methodology): “This mode is actually an asymmetrical DG mode of operation [1].”
Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs (2005, background): “DG (ADG) devices [9] with clean interfaces, in (6).”
Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs (2002, background): “The asymmetrical DG MOSFET has inherent design flexibility with regard to adjustment, parasitics control, and SCE suppression [ 16 ].”