Graphite: A distributed parallel simulator for multicores

By Jason E. Miller, H. Kasture, George Kurian, Charles Gruenwald, N. Beckmann, Christopher Celio, J. Eastep, Anant Agarwal. International Symposium on High-Performance Computer Architecture, 2010

548 citations recorded by the source corpus.

This paper introduces the Graphite open-source distributed parallel multicore simulator infrastructure. Graphite is designed from the ground up for exploration of future multi-core processors containing dozens, hundreds, or even thousands of cores. It provides high performance for fast design space exploration and software development. Several techniques are used to achieve this including: direct execution, seamless multicore and multi-machine distribution, and lax synchronization. Graphite is capable of accelerating simulations by distributing them across multiple commodity Linux machines. When using multiple machines, it provides the illusion of a single process with a single, shared address space, allowing it to run off-the-shelf pthread applications with no source code modification. Our results demonstrate that Graphite can simulate target architectures containing over 1000 cores on ten 8-core servers. Performance scales well as more machines are added with near linear speedup in many cases. Simulation slowdown is as low as 41× versus native execution.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/f7d44175de8404eafd068adca62d4944d9dd0925

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Citations in the corpus

An Evaluation of High-Level Mechanistic Core Models (2014, methodology): “A one-IPC core model is a cycle-by-cycle simulation technique where the core model executes a single instruction per cycle in the absence of long-latency miss events, like long-latency loads or front-end cache misses and branch mispredictions [Jaleel et al. 2008; Miller et al. 2010].”
ZSim: fast and accurate microarchitectural simulation of thousand-core systems (2013, background): “With chips that feature hundreds of threads and cores already on the market [45, 48], developing simulation techniques that scale eﬃciently into the thousands of cores is critical.”
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling (2012, methodology): “When integrated with an architectural simulator [6] [7], DSENT can be used to generate traffic-dependent power-traces and area estimations for the network [8].”
Staring into the Abyss: An Evaluation of Concurrency Control with One Thousand Cores (2014, methodology): “Since many-core chips do not yet exist, we performed our analysis through Graphite [30], a CPU simulator that can scale up to 1024 cores.”
Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation (2011, methodology): “Graphite [22], which forms the basis of the simulator used in this work and which we describe in more detail later, offers three CPU performance models that could be classified as one-IPC models.”