A digital CMOS design technique for SEU hardening

By M. Baze, S. Buchner, D. McMorrow. 2000

135 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/2c9a36404a4e1098fa53cecd2e63d4d0a2c42e1b

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Robert C. Baumann
2. Paul E. Dodd
3. Lloyd W. Massengill
4. J. Schwank
5. D. Fleetwood
6. Michael Nicolaidis
7. Pascale Gouker
8. Véronique Ferlet-Cavrois

Citations in the corpus

• SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments (2001, background): “Other techniques to decrease soft error sensitivity include circuit design techniques that lead to increased transistor counts and layout area [6], [7].”
• Radiation-induced soft errors in advanced semiconductor technologies (2005, background): “Well-based mitigation technologies have also been suggested for CMOS logic [38].”
• Basic mechanisms and modeling of single-event upset in digital microelectronics (2003, background): “Circuit designs that are inherently radiation resistant (known as hardening by design, or HBD) are receiving considerable attention [25,26].”