The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction
By R. Baumann. Digest. International Electron Devices Meeting,, 2002
337 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/21905709cb224840436ffa0456e2f40a24cfad30
How researchers see this paper
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In Electrical and Electronic Engineering
- Lloyd W. Massengill
- Pascale Gouker
- Véronique Ferlet-Cavrois
- Paul E. Dodd
- M. Shaneyfelt
- J. Schwank
- J. Felix
- Norbert Seifert
In Hardware and Architecture
- Paul E. Dodd
- Pascale Gouker
- Véronique Ferlet-Cavrois
- Lloyd W. Massengill
- Norbert Seifert
- J. Felix
- David Atienza Alonso
- Francky Catthoor
Citations in the corpus
- Single Event Transients in Digital CMOS—A Review (2013, background): “rate higher than that due to other reliability mechanisms [53].”
- OCEAN (2014, methodology): “( S CH , N CH ) To simplify solving this optimization problem, we fix the expected error rate to the worst-case rate, which is dependent on technological-and operational-related aspects [Baumann 2002].”
- Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices (2006, background): “charge collection areas) of the devices [2,3].”
- Production and propagation of single-event transients in high-speed digital logic ICs (2004, result): “As noted by Baumann [28] and Benedetto et al. [11], it is only when upsets in latches themselves are mitigated (e.g., by error correction or hardened latch designs) that errors due to the capture of logic transients can be conclusively observed.”
- Characterization of soft errors caused by single event upsets in CMOS processes (2004, background): “There were no significant modifications to the SRAM cell design, which resulted in a slow increase in the SER/bit and a rapid increase in the chip-level SER due to a rising number of bits per chip [88].”
- Basic mechanisms and modeling of single-event upset in digital microelectronics (2003, background): “Commercial DRAMs have generally exhibited a fairly constant SEU performance because DRAM manufacturers have intentionally maintained the unit cell capacitance through the use of clever modifications to the storage cell [66,178].”