Virtualizing transactional memory

By Ravi Rajwar, Maurice Herlihy, Konrad Lai. International Symposium on Computer Architecture, 2005

650 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/7efc7844b3d4f7dc957cc22ad6977037ec7c19af

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

In Hardware and Architecture

Citations in the corpus

An Improved Construction for Counting Bloom Filters (2006, methodology): “Counting Bloom filters have been explicitly used in several papers, including for example [7, 8, 9, 10, 12, 18, 19].”
McRT-STM: a high performance software transactional memory system for a multi-core runtime (2006, neutral): “Runtime transactional memory primitives can be provided either by hardware [16][25][ 19 ][9] (HTM) or by software [1][9][14][17] (STM) with both approaches having their pros and cons.”
An effective hybrid transactional memory system with strong isolation guarantees (2007, positive): “There are several proposed techniques that virtualize HTM systems using structures in virtual memory [21, 8, 7].”
LogTM-SE: Decoupling Hardware Transactional Memory from Caches (2007, neutral): “B = block other transactions VTM [25] - - - S S SC S S S SWV”
Transactional Memory, 2nd edition (2010, background): “’s Virtual Transactional Memory (VTM) proposal [251] took a slightly different approach for accessing and managing metadata.”
LogTM: log-based transactional memory (2006, positive): “On cache overflows, VTM writes the new (and a second copy of old) values to an in-memory table (XADT).”
Hybrid transactional memory (2006, positive): “Recent proposals for “unbounded” HTM [3, 7, 22, 23, 27] aim to overcome the disadvantages of simple bounded HTM designs by allowing transactions to commit even if they exceed on-chip resources and/or run for longer than a thread’s scheduling quantum.”
Transactional Locking II (2006, neutral): “Providing large scale transactions in hardware tends to introduce large degrees of complexity into the design [1–4].”
The evicted-address filter: A unified mechanism to address both cache pollution and thrashing (2012, neutral): “Several previous works [8, 29, 33, 40] have proposed the use of Bloom Vlters in hardware for various applications.”
Bulk Disambiguation of Speculative Threads in Multiprocessors (2006, neutral): “, [2, 12, 13, 18, 20]), threads are typically obtained from a parallel program, and become speculative when they enter a transaction.”
Transactional memory (2010, background): “Transactional memory [5, 6, 7, 8] has been proposed as an alternative to the traditional lock-based approach to express and manage concurrency.”