Unbounded transactional memory

By C. Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, Sean Lie. International Symposium on High-Performance Computer Architecture, 2005

555 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Experimental and Cognitive Psychology

View Paper: https://www.semanticscholar.org/paper/19710fa0e64f36616e112c8a7b4e99ba4cb43c74

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Håkan Grahn
2. T. Harris
3. J. Larus
4. Ravi Rajwar
5. Maurice Herlihy
6. Nir Shavit
7. Eric Koskinen
8. Keshav Pingali

In Experimental and Cognitive Psychology

1. Håkan Grahn
2. T. Harris
3. Ravi Rajwar
4. J. Larus
5. Eric Koskinen
6. Maurice Herlihy
7. Nir Shavit
8. Chi Cao Minh

Citations in the corpus

• Transactional Memory, 2nd edition (2010, background): “describe a register recovery implementation based on a physical register file [15].”
• Learning from mistakes: a comprehensive study on real world concurrency bug characteristics (2008, unknown): “Along this direction, transactional memory (TM) [1,2,15,16,25,26,27,36] is one of the popular trends.”
• Transactional memory (2010, methodology): “Examples of hardware trans-actional memory proposals supporting virtualization are UTM [17], VTM [25], and XTM [26].”
• Bulk Disambiguation of Speculative Threads in Multiprocessors (2006, methodology): “, [2, 12, 13, 18, 20]), threads are typically obtained from a parallel program, and become speculative when they enter a transaction.”
• Transactional boosting: a methodology for highly-concurrent transactional objects (2008, methodology): “This approach has been investigated in hardware [1, 8, 14, 24, 23], in software [9, 10, 13, 21, 31], and in schemes that mix hardware and software [6, 28].”
• Transactional Locking II (2006, background): “Providing large scale transactions in hardware tends to introduce large degrees of complexity into the design [1–4].”
• Hybrid transactional memory (2006, background): “Based on studies in the literature [3, 7, 23], we expect that in many cases almost all transactions will not overflow on-chip resources, and thus neutered performance will closely track unneutered performance, even for more realistic codes.”
• AVIO: detecting atomicity violations via access interleaving invariants (2006, unknown): “Recently there is an emerging trend toward transactional memory programming model via hardware or software support [1, 13, 16, 18].”
• Optimistic parallelism requires abstractions (2007, background): “There is growing interest in supporting transactions efficiently with software and hardware implementations of transactional memory [1, 12, 13, 21, 34].”
• LogTM-SE: Decoupling Hardware Transactional Memory from Caches (2007, background): “e, support cache victimization, unbounded nesting, thread suspension/migration, and paging [3, 25].”
• LogTM: log-based transactional memory (2006, methodology): “’s Large Transactional Memory (LTM) [2] uses lazy version management and eager conflict detection.”
• Virtualizing transactional memory (2005, unknown): “This mode is based on mechanisms proposed by prior work [2, 7, 10, 20], and this mode's performance effectively determines the performance of the overall scheme.”